End-to-end emulator-confirmed: 2.23 detects Videx as Pascal 1.1, 2.20 doesn't
The cpm-videx investigation’s central finding has always been: 2.23 added 11 bytes that check $Cn0B for the Pascal 1.1 marker; 2.20 doesn’t. That gives Videx a different device code in 2.23 than in 2.20, which routes it to a different BIOS handler. Until today this was provable from static disassembly only. Now it’s emulator-verified.
What changed
Stage-2’s emu_softcard_full.py learned to install a Videx Videoterm ROM in slot 3, sourced from the a2fpga repo’s Videx Videoterm ROM 2.4.bin (1024 bytes). The standard mapping:
$C300-$C3FF(slot ROM): bytes 768-1023 of the image (the last 256 bytes, mirrored from$CB00-$CBFF)$C800-$CBFF(expansion ROM): bytes 0-1023 of the image
That puts the right Pascal-firmware ID bytes at the right offsets:
$C305 = $38 (Pascal 1.0 ID byte 1)
$C307 = $18 (Pascal 1.0 ID byte 2)
$C30B = $01 (Pascal 1.1 marker)
The slot scanner now sees it
Running both versions through the slot scanner with this Videx in slot 3 and the Disk II PROM in slot 6:
2.23 with Videx in slot 3:
slot 3: $06 <- Pascal 1.1, the new code introduced in 2.23
slot 6: $02 (Disk II)
2.20 with Videx in slot 3:
slot 3: $04 <- Pascal 1.0 only; 2.20 doesn't check $C30B
slot 6: $02 (Disk II)
The device-code-4 storage at $03BB for 2.20 is exactly what causes the hang documented in the v2.20 hang byte-trace: 2.20’s BIOS dispatch table maps device code 4 to handler $DFBE, which is the broken path. 2.23’s device code 6 maps to a different handler that uses the Pascal 1.1 vector table at $Cn0D-$Cn10.
What this confirms
- The 11-byte branch in 2.23’s slot scanner actually fires on a real Videx ROM, not just on synthetic test bytes.
- The Videx ROM 2.4 binary from a2fpga genuinely has the Pascal 1.1 marker
$01at offset$0B. (Older Videx ROMs predating Pascal 1.1 wouldn’t.) - The
$03B8-$03BFslot-info table that the BIOS dispatch consults is populated correctly in both versions; the routing difference is downstream of detection, not in detection.
Status
Detection settled end-to-end. Stage-3 work continues with: implementing IX/IY (DD/FD-prefix) opcodes in the Z-80 emulator so the cold-boot generator can run, modeling a bidirectional CPU switch for the cooperative-CPU disk path, then booting through to the BIOS-handler-build step where the 2.20 hang surfaces.