CI/CD attempt — OSS toolchain doesn't produce a usable bitstream

Tried setting up a GitHub Actions CI pipeline using the open-source Yosys/nextpnr/apicula toolchain so that pushes could at least get a synthesis check without requiring the proprietary Gowin IDE.

Synthesis completes. The OSS tools parse the SystemVerilog, resolve the module hierarchy, and produce a netlist without errors. But the place-and-route output is not accepted by the Gowin programmer — the generated bitstream format is either incompatible or not recognized as valid for the GW2AR-18C.

Spent time with the apicula/gowin backend documentation and tried several variations in the build flow. Nothing produced a .fs file that the Gowin programmer would flash. The proprietary Gowin IDE (V1.9.8.11 Education Edition) remains the only toolchain that produces a correct, flashable bitstream for this device.

Shelving the CI effort. The Gowin IDE is not available for automated environments and there is no open-source alternative that closes the loop to a programmable bitstream. Build and test remain local-only.